1. Field of the Invention
The present invention relates to a transistor which is field-shield-isolated from surrounding regions.
2. Description of the Background Art
FIG. 18 is a plan view showing an application of the conventional field shield isolation technique to a gate array. FIG. 19 is a cross-sectional view taken along the line XIX--XIX of FIG. 18. For the purpose of avoiding the complication of illustration, a gate oxide film 3 to be described later is not shown in FIG. 18.
A silicon layer 2 having an SOI structure is formed on a buried oxide layer 1. Oxide films 61 and 62 are formed on the silicon layer 2, and a pair of field shield gate electrodes 41 and 42 are buried in and surrounded by the oxide films 61 and 62, respectively. Contact pads 51a and 51b of gate electrodes 5a and 5b are formed on parts of the oxide film 61 which are positioned over the field shield gate electrode 41, and contact pads 52a and 52b of the gate electrodes 5a and 5b are formed on parts of the oxide film 62 which are positioned over the field shield gate electrode 42.
The gate electrode 5a further includes a coupling portion 53a for coupling the contact pads 51a and 52a to each other. The gate electrode 5b further includes a coupling portion 53b for coupling the contact pads 51b and 52b to each other.
The gate oxide film 3 is provided between adjacent respective edges S1 and S2 of the oxide films 61 and 62. Diffusion layers 21, 22, 23 serving as either of a drain and a source are formed in part of the silicon layer 2 which is under the gate oxide film 3 and is not immediately under the coupling portions 53a and 53b.
The diffusion layers 21, 22 and the coupling portion 53a form a MOS transistor, and the diffusion layers 22, 23 and the coupling portion 53b form a MOS transistor. These MOS transistors are isolated from left-hand and right-hand external regions of FIG. 18 by applying a predetermined potential to the field shield gate electrodes 41 and 42.
In the conventional field shield isolation technique applied to the gate array, when attention is focused on the gate electrode 5a, the contact pads 51a and 52a are positioned within respective regions immediately over the field shield gate electrodes 41 and 42. More specifically, the left-hand edge E1 of the contact pad 51a is positioned a distance d1 to the right of the left-hand edge F1 of the field shield gate electrode 41; the right-hand edge E2 of the contact pad 51a is positioned a distance d2 to the left of the right-hand edge F2 of the field shield gate electrode 41; the left-hand edge E3 of the contact pad 52a is positioned a distance d3 to the right of the left-hand edge F3 of the field shield gate electrode 42; and the right-hand edge E4 of the contact pad 52a is positioned a distance d4 to the left of the right-hand edge F4 of the field shield gate electrode 42. The distances used herein mean differences in lateral positions (positions as viewed in the rightward and leftward directions) in plan view. In other words, the distances mean those within the plane in which the silicon layer 2 extends as viewed in the direction perpendicular to this plane or in the direction of the thickness of the silicon layer 2. This definition is used also in the following description.
The field shield gate electrodes 41, 42 and the gate electrodes 5a, 5b which are fabricated in different fabrication steps must be brought into positional alignment with each other. Thus, the distances d1 to d4 have been used as margins so that the contact pads 51a, 51b, 52a, 52b are positioned immediately over the field shield gate electrodes 41, 42.
However, the use of such margins increases the lateral size of the structure, resulting in ineffective use of the chip area thereof, that is, the increase in chip area.